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AD9467BCPZ-250

发布时刻:2019/6/21 11:55:00 拜访次数:100 发布企业:深圳市旺财半导体有限公司

16-Bit, 250 MSPS Analog-to-Digital Converter Enhanced Product AD9467-EP FEATURES 75.5 dBFS SNR to 210 MHz at 250 MSPS 90 dBFS SFDR to 300 MHz at 250 MSPS 60 fs rms jitter Excellent linearity at 250 MSPS DNL = ±0.5 LSB typical INL = ±3.5 LSB typical 2 V p-p to 2.5 V p-p (default) differential full-scale input (programmable) Integrated input buffer External reference support option Clock duty cycle stabilizer Output clock available Serial port control Built-in selectable digital test pattern generation Selectable output data format LVDS outputs (ANSI-644 compatible) 1.8 V and 3.3 V supply operation ENHANCED PRODUCT FEATURES Extended temperature range (−55°C to +125°C) Controlled manufacturing baseline Qualification data available on request APPLICATIONS Multicarrier, multimode cellular receivers Antenna array positioning Power amplifier linearization Broadband wireless Radar Infrared imaginCommunications instrumentation GENERAL DESCRIPTION The AD9467-EP is a 16-bit, monolithic, IF sampling analog-todigital converter (ADC). It is optimized for high performance over wide bandwidths and ease of use. The product operates at a 250 MSPS conversion rate and is designed for wireless receivers, instrumentation, and test equipment that require a high dynamic range. The ADC requires 1.8 V and 3.3 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are LVDS-compatible (ANSI-644- compatible) and include the means to reduce the overall current needed for short trace distances. FUNCTIONAL BLOCK DIAGRAM 16 2 16 2 PIPELINE ADC CLOCK AND TIMING MANAGEMENT REF LVDS OUTPUT STAGING AVDD1 (1.8V) DRVDD (1.8V) AVDD2 (3.3V) AVDD3 (1.8V) SPIVDD (1.8V TO 3.3V) AGND XVREF DRGND AD9467-EP BUFFER VIN+ CLK+ CLK– VIN– CSB SDIO SCLK OR+/OR– D15+/D15– TO D0+/D0– DCO+/DCO– 1 4 7 5 1 -0 0 1 Figure 1. A data clock output (DCO) for capturing data on the output is provided for signaling a new output bit. The internal powerdown feature, when enabled via the serial port interface (SPI), typically consumes less than 5 mW. Optional features allow users to implement various selectable operating conditions, including input range, data format select, and output data test patterns. The AD9467-EP is available in a Pb-free, 72-lead, LFCSP specified over the −55°C to +125°C extended temperature range. Additional application and technical information can be found in the AD9467 data sheet. PRODUCT HIGHLIGHTS 1. IF optimization capability used to improve SFDR. 2. Outstanding SFDR performance for IF sampling applications such as multicarrier, multimode 3G, and 4G cellular base station receivers. 3. Ease of use: on-chip reference, high input impedance buffer, adjustable analog input range, and an output clock to simplify data capture. 4. Packaged in a Pb-free, 72-lead LFCSP package. 5. Clock duty cycle stabilizer (DCS) maintains overall ADC performance over a wide range of input clock pulse widths. 6. Standard SPI supports various product features and functions, such as data formatting (offset binary, twos complement, or Gray coding).

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